This invention relates to a current generator circuit having a wide frequency response.
In particular, this circuit is of the type which comprises at least one current mirror formed of MOS transistors, being powered through a terminal held at a constant voltage, having an input leg which includes at least a first diode-connected transistor through which a reference current is forced by a first current generator coupled to a first terminal of the first transistor, and having an output leg which includes at least a second transistor to generate, onto an output terminal of the mirror coupled to a first terminal of the second transistor, a mirrored current which is proportional to the reference current. A control terminal of the first transistor is coupled to a corresponding control terminal of the second transistor. The first and second transistors also have respective second terminals connected to the terminal held at the constant voltage.
Reference will be specifically made herein, for illustration purposes only, to a voltage regulator having an output stage formed by a circuit as described above and useful, for example, in a driving system for automotive audio devices.
As is well known, the connection of two transistors into a so-called "current mirror" configuration is frequently employed in the design of electric circuits, in particular as integrated monolithically. This configuration allows a current to be transferred to an output leg from an input leg while retaining the same flow direction for the current. The current which is flowing through the input leg may be, for example, that supplied by a reference current generator. The output current will be proportional to the input current by a predetermined factor, which may be equal to unity but more commonly has a much greater value than unity and is determined by the ratio of the device dimensions. The ratio of the output leg current to the input leg current is, therefore, equal to that constant factor, and is called the mirror ratio.
This configuration, whereby a current with a predetermined value can be obtained, is a basic one in so-called current generator circuits. The latter may include a mirror circuit of varying complexity, or alternatively, a number of mirror circuits cascade-connected with one another.
One exemplary application of a circuit arrangement of this kind is to driver circuits for an electric load using a power type of driving transistor connected directly to the load. In this case, the power transistor represents the output end of a more complicated circuit, such as a voltage regulator. In order to make the output current stable, the transistor is connected into a mirror configuration with an additional transistor provided upstream.
Conventional types of current mirror circuits are analytically reviewed, for example, in a book by P. R. Gray and R. G. Meyer entitled "Analysis and Design of Analog Integrated Circuits", Wiley, New York, 1984, at pages 233-246 and 703-718, which is hereby incorporated by reference. Other basic and general background may be found in the following books, all of which are hereby incorporated by reference: the ANALOG CIRCUIT DESIGN SEMINAR books published by Analog Devices; ANALOG CIRCUIT DESIGN (ed. J. Williams 1991); Analog Dialogue from 1980 to date; Collins, ANALOG ELECTRONICS HANDBOOK (1989); Coughlin and Driscoll, OP AMPS AND LINEAR INTEGRATED CIRCUITS 3.ed.(1991); Davidse, INTEGRATION OF ANALOGUE ELECTRONIC CIRCUITS; Feucht, HANDBOOK OF ANALOG CIRCUIT DESIGN (1990); Geiger et al., VLSI DESIGN TECHNIQUES FOR ANALOG AND DIGITAL CIRCUITS; Gray & Meyer, ANALYSIS & DESIGN OF ANALOG INTEGRATED CIRCUITS (2.ed. 1983 and 3.ed. 1993); Grebene, BIPOLAR & MOS ANALOG IC DESIGN (1984); Haskard and May, ANALOG VLSI DESIGN (1987); L. P. Huelsman, and P. E. Allen, INTRODUCTION TO THE THEORY AND DESIGN OF ACTIVE FILTERS (1980); Moschytz, LINEAR INTEGRATED NETWORKS: DESIGN (1975); Moschytz, LINEAR INTEGRATED NETWORKS: FUNDAMENTALS (1974); Pease, TROUBLESHOOTING ANALOG CIRCUITS; Schaumann et al., DESIGN OF ANALOG FILTERS (1990); J. Scott, ANALOG ELECTRONIC DESIGN (1991); Soclof, "Design and Applications of Analog Integrated Circuits"; Toumazou et al., ANALOGUE IC DESIGN: THE CURRENT-MODE APPROACH; Van Valkenburg, ANALOG FILTER DESIGN (1982); Thomas Young, LINEAR INTEGRATED CIRCUITS (1981).
In general, such circuits can be implemented using either bipolar transistors or transistors of the MOS type.
As explained in detail in the above reference, a current mirror comprises, in its most basic form, only two transistors and a current generator which supplies the current to be transferred to the output, that is the reference current, as previously mentioned. The generator can be implemented, for instance, by a resistor connected to a terminal of a voltage supply and to one of the transistors which forms the input transistor.
This circuit arrangement is quite simple, and is used in circuits which have no strict requirements in terms of accuracy. Other, more elaborate and just as well known configurations, such as that commonly referred to as Wilson's--involving the provision of additional transistors--are used in more sophisticated designs.
Furthermore, mirror circuits of the bipolar type usually require a small triggering voltage and pose no problems of response speed, but need comparatively large currents for their turn-on. By contrast, mirror circuits of the MOS type, when including a power type of output transistor, do have response problems at high frequencies.
For a specific application, the choice between bipolar and MOS transistors is determined by different factors, both in terms of manufacturing process and of electric characteristics.
Within the scope of the present invention, reference will be made in particular to current mirror arrangements of the MOS type. Both P-channel MOS transistors, abbreviated to P-MOS, and N-channel MOS transistors, briefly N-MOS, will be considered on equal terms.
Shown in FIG. 1 is a typical arrangement for the simplest of conventional current mirror generator circuits of the MOS type, basically comprised of a transistor pair and a current generator. By way of example, the transistors shown in that Figure are in particular of the P-channel MOS type. The mirror circuit is generally denoted in the Figure by the reference numeral 1.
The current mirror 1 comprises a diode-connected input transistor M1, that is a transistor which has a gate terminal Gal shorted to a drain terminal D1. The drain terminal D1 of M1 is further connected to a supply terminal, specifically a ground terminal, which forces a current I1 to flow through M1. This current, which represents the input current to the mirror 1, is constant and has a predetermined value. The transistor M1 forms, in combination with the generating stage G1, the input leg of the mirror 1.
A second output transistor M2 has a gate terminal Ga2 connected to the gate terminal Gal of the first transistor, M1. A drain terminal D2 of M2 is connected to an output terminal OUT of the circuit 1. The transistor M2 forms the output leg of the mirror, through which the current generated by the circuit and supplied to its output is caused to flow. This current is schematically indicated in the Figure by an arrow lout.
The transistors M1 and M2, being in a mirror configuration, are coupled together through their respective gate terminals, Ga1 and Ga2.
Furthermore, both transistors, M1 and M2, are powered through their respective source terminals, S1 and S2, which are held at the same constant voltage. In particular, and as shown in FIG. 1, the source terminals S1 and S2 are connected to a supply line, schematically denoted by Vbat, which may represent the connection to one pole of a source of constant voltage, such as the battery of a motor vehicle.
In steady-state operation of the circuit shown in FIG. 1, since the transistor M1 has its gate and drain shorted together, the gate-source voltage Vgs exceeds the threshold value of the transistor, which is tied to the transistor's own construction. Thus, the transistor will be operating in saturation and the current I1 supplied by the generator G1 will be flowing through it. Since the transistors M1 and M2 have their gate terminals Ga1 and Ga2 connected to each other and both their respective source terminals S1 and S2 connected to Vbat, the transistor M2 will have the same gate-source voltage as the transistor M1. A mirrored current, that is the output current lout whose value is proportional to that of the input current I1 according to mirror ratio, as previously mentioned, will be flowing through it.
Specifically, in a case where the circuit has been integrated, the mirror ratio between the output current and the input current would be equal to the ratio between the quantities (W/L)2 and (W/L)1 for the transistors M2 and M1, respectively, where W is the channel width and L the channel length. In general, the size of M2 relative to M1 increases proportionally with the value of the mirror ratio.
Also shown, in FIG. 2, for completeness' sake, is a current mirror circuit, again generally denoted by 1, which is similar to that shown in FIG. 1 but in which the MOS transistors are of the N-channel type, so that the signs of the voltages are reversed. The source terminals S1 and S2 of the transistors M1 and M2 are here connected to a ground terminal, and the current generator G1 is connected between the supply terminal and the drain terminal D1 of the transistor M1.
The circuit depicted in FIG. 2 operates in an equivalent manner to that shown in FIG. 1, however, the respective currents flow in opposite directions.
The current mirror circuit 1 just described shows, however, certain drawbacks in the respect of its frequency response.
Prior to undertaking a detailed analysis of the circuit, note that MOS transistors have at their gate terminals an effective intrinsic capacitance which is non-zero and can cause delays in the transistor operation. More specifically, in the construction of a MOS transistor, whether of the N-channel or P-channel type, two capacitances are to be found, as seen from the gate terminal, namely a gate-to-source capacitance Cgs and a gate-to-drain capacitance Cgd. The values of these capacitances are proportional to the source and drain areas of the transistor.
Referring to current mirror circuits wherein the value of the mirror ratio is fairly large, for the applications encompassed by the present invention, the capacitances of the smaller transistor, i.e. the input transistor, are negligible compared to the corresponding intrinsic capacitances of the output transistor, which transistor may commonly be a power transistor, as mentioned above. In this respect, it is assumed that the area, say equal to unity, of the transistor M1 is much smaller than the area of the transistor M2, assumed to be equal to the mirror ratio X. Only the gate-to-source and gate-to-drain capacitances of the last-mentioned transistor have been indicated in dash lines and briefly denoted by Cs and Cd, respectively, in FIGS. 1 and 2.
The presence of the dominate capacitance Cs, which increases in value with an increase in the mirror ratio (and corresponding increase in the size of M2), contributes greatly to the aformentioned problems. As can be easily construed from an analysis of the frequency stability of the circuit according to FIGS. 1 and 2, its transfer function, i.e. the mathematical law that governs the output-to-input signal relation, has at a certain frequency a pole which is determined by the presence of the intrinsic capacitances on the gate of M2. As is known, the pole has the effect of depressing the circuit gain from that frequency at a constant rate of attenuation.
The so-called cutoff frequency f1 introduced by the pole into the mirror circuit of FIGS. 1 and 2 specifically is f1=(1/2.pi.).times.gm.sub.M1 /(Cs+Cd), where gm.sub.M1 is the transconductance of the transistor M1. The term Cs+Cd is easily explained as being the effective overall capacitance--seen from the gate terminal of M2 whence the two capacitances would appear to be in parallel, so to speak. Since Cs is much greater than Cd, the sum of Cs+Cd is essentially equal to Cs; and with Cs being a fairly large value, the cutoff frequency f1 will be relatively low, on the order of hundreds of kHz.
More poles would also be present, of necessity, in the overall transfer function which characterizes the circuit and its specific application. For example, an electric load is connected to the output OUT of the mirror circuit 1, as previously mentioned, which load can be outlined by the series connection of a resistive load with a capacitive load. Thus, the presence of a capacitive load on the terminal OUT creates a further pole in the transfer function.
The simultaneous presence of two poles can produce instability in the circuit operation, in cases where the circuit is inserted in a feedback loop, as is well known to those skilled in the art. A critical situation occurs when the respective cutoff frequencies lie sufficiently close together to cause the combined effects of both poles, which are manifested by a doubled gain falling rate, to become substantial before the gain has dropped down to a unity value.
With reference to the current mirror of FIGS. 1 and 2, the load applied to the output OUT usually has a large capacitive value. Accordingly, it introduces a pole at a fairly low frequency f2, again on the order of hundreds of kHz. In addition, the value of f2 shifts according to the applied load. On the other hand, the pole relating to the gate capacitances of the transistor M2 is, as already mentioned, at an equally low frequency, higher than but close to that due to the load. The frequency of the pole introduced by M2, moreover, approximates that due to the load as the area of M2 and the mirror ratio increase.
Thus, the operation of the conventional current mirror circuit as illustrated by FIGS. 1 and 2 shows some instability due to the presence of a large capacitance on the control node of the output transistor M2. This capacitance is also responsible for delays in the steady state operation of the circuit.
The technical problem underlying this invention is to provide a current generator circuit of the current mirror type, whereby the adverse effect of the intrinsic capacitance on the gate node of the output transistor can be made negligible. The circuit forming the subject of this invention should have an extended range of frequency response.
Another object of the invention is to provide a current mirror circuit of simple construction which can be manufactured by a process of least complexity, and which, when integrated monolithically, would occupy a reduced integration area, while assuring satisfactory performance.
Innovative Current Mirror
The solvent idea on which this invention is predicated is one of providing a current generator circuit of the current mirror type, whereby the effective overall capacitance present on the control node of the output transistor of the current mirror can be controlled, and in particular, made lower in value than the intrinsic capacitance anyhow present on that same node. To this aim, an element is provided which drives the node with a selected impedance.
A current generator circuit having a controllable frequency response comprises at least one current mirror of the MOS transistor type. The current mirror has an input leg which includes at least a first diode-connected transistor, and an output leg which includes at least a second transistor. A reference current is forced through the first transistor by means of a first current generator which is coupled to a first terminal of the transistor, specifically a drain terminal thereof. The two transistors have respective control terminals, i.e. gate terminals, which are coupled together. The mirror generates, on an output terminal thereof which is coupled to a first or drain terminal of the second transistor, a mirrored current which is proportional to the aforementioned reference current.
Furthermore, the current mirror is powered through a terminal which is held at a constant voltage; in particular, the first and second transistors have respective second terminals, namely their source terminals, which are held at this constant voltage.
In accordance with the invention, an impedance matching means is connected between the control terminals of the first and second transistors. This means is arranged to hold both control terminals at the same voltage level, so that the current mirror can properly operate.
Also in accordance with the invention, the impedance matching means preferably comprises a voltage follower having a first input, namely an input of the non-inverting type, connected to the gate terminal of the first transistor, and an output connected to the gate terminal of the second transistor and feedback-connected to a second input, specifically an input of the inverting type, of the follower.
In essence, the impedance matching means has an output impedance which can be adjusted, and in particular--for the primary purpose of this invention--has a lower value than would be the case without this means. It functions to regulate the impedance on the control node of the output transistor, i.e. the second transistor.
Particularly in a preferred embodiment of the invention, the voltage follower comprises a third transistor which functions as a low output impedance amplifying element connected with its output to the gate of the second transistor, and a fourth transistor which is connected to the first transistor of the mirror and configured to act as a mirror with the third, whereby the gate terminals of the first and second transistors will be held at the same potential.
This invention can be applied equally well to MOS transistors of the N-channel and P-channel types.
Based on the solvent idea, the technical problem is solved by a current generator circuit having a controllable frequency response, as described herein and defined in the appended Claims.
The problem is also solved by a method of generating at a controlled rate a mirrored current from a reference current, as described herein and defined in the appended Claims.